Sercos Intl.has introduced the Sercos EasySlave, an FPGA-based single-chip controller for simple Sercos III slave devices. It has a real time channel with one input and one output connection, and supports cycle times as low as 31.25 usec. An IP core is provided as a netlist for the Xilinx Spartan-6 FPGA family. The IP core contains all the functions of a Sercos slave connection, including the associated software library for I/O devices (e.g., analog inputs, encoders). I/O applications are synchronized in the Sercos cycle. "Sercos EasySlave can be integrated in an application with minimal effort in order to achieve various I/O activations," according to Peter Lutz, Managing Director of Sercos Intl
Technical support for the EasySlave is provided by Steinbeis Transfer Center for Systems Technology (TZS) in Esslingen, Germany. TZS offers an EasySlave evaluation kit to facilitate a quick and easy introduction to Sercos slave development. The evaluation kit includes a development board based on a Xilinx Spartan-6 XC6SLX9 FPGA and can be extended using plug-in modules. The evaluation kit includes all other required material and documents (Ethernet cable, power supply, and documentation).
"The EasySlave evaluation kit makes Sercos III slave development easy. Steinbeis-TZS will be happy to provide assistance in the integration and commissioning of EasySlave,"" states Professor Reinhard Keller of Steinbeis-TZS.
Various EasySlave licensing models are available from Sercos Intl., with Sercos member companies offered special prices. In addition, a license-free bitstream IP core version with a limited functionality is available, under the product name EasySlave-IO.